Integrated circuit design is constantly being scaled down in pursuit of faster circuit operation and lower power consumption. Scaled dimensions in a circuit design generally requires attendant changes in fabrication processing.
A basic building block of integrated circuits is the thin film transistor (TFT). As is known in the art, the transistor typically includes a gate electrode separated from a semiconductor layer or substrate by a thin gate dielectric material. Although a common acronym for state-of-the-art transistors is MOS, for metal-oxide-silicon, the material of choice for the gate electrode has long been silicon rather than metal. Among other advantages, silicon gate electrodes are able to withstand high temperature processes and enable self-aligned doping processes used for completing the transistor, thus saving expensive masking steps.
Accordingly, conventional gate electrodes are formed of polysilicon doped with conductivity-enhancing impurities, such as arsenic, phosphorus or boron. Silicon can be deposited by CVD with in situ doping by flowing a dopant source gas (e.g., arsine, phosphine, diborane, etc.) concurrently with a silicon source gas (e.g. silane). Recently, interest has been drawn to the possibility of doping silicon electrodes with germanium, thereby reducing the electrical work function of the transistor gate electrode. Accordingly, a reduced voltage is needed to operate the circuit, consequently generating less heat. Moreover, a silicon germanium gate electrode remains compatible with surrounding materials and current integrated circuit fabrication processes. Proposals for forming silicon germanium layers include in situ doping of a silicon layer by forming germane (GeH4) along with silane (SiH4) in a chemical vapor deposition (CVD) process.
While in situ doped CVD processes have been found to be effective in producing silicon germanium, the addition of germane to the silane flow has been found to significantly increase incubation or nucleation times over dielectric materials, particularly oxides such as silicon dioxide and some of the high-k materials discussed below. Similarly slow nucleation over dielectric materials occurs when chemical vapor depositing other gate electrode materials, such as polysilicon and particularly silicon in situ doped by flowing dopant source gases (e.g., diborane, arsine or phosphine) along with a silicon source.
Slow nucleation entails longer overall deposition times, lower throughput and consequently greater fabrication costs. The semiconductor industry is very sensitive to fabrication costs. Accordingly, any increase in wafer throughput, at any stage of processing, translates to reduced production costs and higher margins.
One way in which SiGe or other in situ doped silicon deposition has been hastened is by the first formation of a nucleation layer, typically silicon, over the gate dielectric, followed by poly-SiGe deposition. This additional step unfortunately complicates the process flow, requires adjustment of the doping concentrations at the dielectric-electrode interface to ensure the desired work function for the transistor, and does not necessarily guarantee rapid and uniform nucleation. Other recent work optimizing silicon and poly-SiGe deposition processes has also focused on increasing deposition rates while maintaining layer uniformity. For example, U.S. Pat. Nos. 5,607,724; 5,614,257; 5,700,520; 5,874,121; and 5,876,797 describe methods of depositing polysilicon at high rates by CVD under “high pressure” conditions.
Another area in which process control is particularly critical is the fabrication of transistor gate dielectrics. In the pursuit of ever faster and more efficient circuits, semiconductor designs are continually scaled down with each product generation. Transistor switching time plays a large role in the pursuit of faster circuit operation. Switching time, in turn, can be reduced by reducing the channel length of the transistors. In order to realize maximum improvements in transistor performance, vertical dimensions should be scaled along with horizontal dimensions. Accordingly, effective gate dielectric thickness, junction depth, etc. will all decrease with future generation integrated circuits. To date, this scaling has reduced gate electrode widths to less than 0.25 μm. Currently, commercial products are available employing gate widths or critical dimensions of 0.18 μm or less.
Conventional gate dielectrics are formed of high quality silicon dioxide and are typically referred to as “gate oxide” layers. Ultrathin gate oxides (less than 7 nm), however, have been found to exhibit high defect densities, including pinholes, charge trapping states, and susceptibility to hot carrier injection effects. Such high defect densities lead to leakage currents through the gate dielectric and rapid device breakdown unacceptable for circuit designs with less than 0.25 μm gate spacing, i.e., sub-quarter-micron technology.
While care under laboratory conditions can be used to control defect densities, such control has been difficult to achieve under commercial volume fabrication conditions. Moreover, even if the integrity of the oxide is perfectly maintained, quantum-mechanical effects set fundamental limits on the scaling of gate oxide. At high fields, direct tunneling dominates over Fowler-Nordheim tunneling, and largely determines oxide scaling limits. These scaling limits have been estimated at about 2 nm for logic circuits, and about 3 nm for more leakage-sensitive memory arrays in dynamic random access memory (DRAM) circuits. See, e.g., Hu et al., “Thin Gate Oxides Promise High Reliability,” SEMICONDUCTOR INTERNATIONAL (July 1998), pp. 215-222.
Another problem with thin gate oxides is their susceptibility to dopant diffusion from the overlying gate electrode. A polysilicon gate electrode layer is typically doped with boron for its enhanced conductivity. As the gate oxide thickness is scaled down, boron can easily penetrate through the gate oxide, resulting in instabilities in device properties. Boron penetration into gate dielectrics has such undesirable consequences as positive shifts in threshold voltage, increases in sub-threshold swing, increases in charge trapping, decreases in low-field hole mobility, and degradation of current drive due to polysilicon depletion in p-MOSFETs.
Some efforts to address deficiencies of silicon dioxide include nitrogen incorporation into the gate dielectric. Silicon nitride (Si3N4) has a higher dielectric constant than SiO2, theoretically enabling thinner equivalent oxide thickness for gate dielectrics that are not tunnel-limited, and furthermore serves as an effective barrier against impurity diffusion. However, the interfaces between silicon nitride films and the underlying semiconductor substrate are generally of poor quality, resulting in a high density of charge trapping sites and pinholes, and attendant current leakage. As a consequence, attempts have been made to create SiO2 and Si3N4 hybrids, such as silicon oxynitride films, for use as gate dielectrics. Conventional methods of incorporating nitrogen into silicon oxide gate dielectrics are difficult to control, however, particularly for ultra-thin gate dielectrics of future generation devices
Other solutions to scaling problems include the use of high permittivity materials (“high k”). Theoretically, incorporating materials of high k materials into the gate dielectric opens the door to further device scaling. Due to higher dielectric constant, many materials can exhibit the same capacitance as a thinner silicon dioxide layer, such that a lower equivalent oxide thickness can be achieved without tunnel-limited behavior. Some high k materials under investigation include aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), barium strontium titanate (BST), strontium bismuth tantalate (SBT), tantalum oxide (Ta2O5), etc. Such dielectrics have a dielectric constant (or k) value greater than about 7. While exhibiting greatly increased dielectric strength, these materials have been difficult to integrate with existing fabrication technology.
Similar high quality, thin dielectric layers are desirable in other contexts of integrated circuit fabrication. Integrated capacitors in memory arrays must exhibit a certain minimum capacitance for proper data storage and retrieval. Some efforts to increase capacitance for a given memory cell space have focused on the use of materials characterized by high dielectric constants (high k materials), such as those listed above.
Accordingly, a need exists for improvements in the integration of dielectric layers and conductors in semiconductor fabrication, particularly at interfaces in transistor gate stacks.